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DSP Reverse

TMS320C6678 DSP Reverse

  Time:2013-04-16 11:51

 

 
 
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The TMS320C6678 Multicore Fixed and Floating Point Digital Signal Processor accepts TI's KeyStone multicore architecture. TI’s KeyStone Multicore Architecture
provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O.
The TMS320C6678 is Integrated with eight C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 10 GHz. 
The TMS320C6678 is widly used for high-performance signal processing applications such as mission critical, medical imaging,
test, and automation. The C6678 platform is power efficient and easy to use. 
 
The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 
there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache.
 
Features of TMS320C6678
• Eight TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each with
1) 1.0 GHz or 1.25 GHz C66x Fixed/Floating-Point CPU Core
 40 GMAC/Core for Fixed Point @ 1.25 GHz
 20 GFLOP/Core for Floating Point @ 1.25 GHz
2) Memory 
  32K Byte L1P Per Core
  32K Byte L1D Per Core
  512K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
1)4096KB MSM SRAM Memory Shared by Eight DSP C66x CorePacs
2)Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
• Multicore Navigator
1)8192 Multipurpose Hardware Queues with Queue Manager
2) Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for 
1) Transport Plane IPsec, GTP-U, SCTP, PDCP
2) L2 User Plane PDCP (RoHC, Air Ciphering)
3) 1 Gbps Wire-Speed Throughput at 1.5 MPackets Per Second
 
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