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DSP Reverse

TMS320C6474 DSP Reverse

  Time:2013-04-16 13:01


TMS320C6474 DSP Reverse,chip crack,TMS320C6474 DSP code extraction,mcu reverse,DSP Crack,PCB copying,chip decryption.
TMS320C6474 device is the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.
The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture developed by TI.The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™
DSP platform.
the C6474 device offers cost-effective solutions to high-performance DSP programming challenges with three independent
DSP subsystems.The C6474 DSP integrates a large amount of on-chip memory organized as a three-level memory system.
The level-1 data memories on the device are 32 KB each.The C64x+ DSP core employs eight functional units, two register files,
and two data paths.
Key Features
High-Performance Multicore DSP (C6474)
Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
Commercial Temperature and Extended Tmperature
3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
Enhanced VCP2/TCP2
Frame Synchronization Interface
16-/32-Bit DDR2-667 Memory Controller
EDMA3 Controller
Antenna Interface
Two 1x Serial RapidIO® Links, v1.2 Compliant
One 1.8-V Inter-Integrated Circuit (I2C) Bus
Two 1.8-V McBSPs
1000 Mbps Ethernet MAC (EMAC)
Six 64-Bit General-Purpose Timers
16 General-Purpose I/O (GPIO) Pins
Internal Semaphore Module non-UMTS Systems
System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller