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DSP Reverse

Microchip dsPIC30F Reverse Decryption

  Time:2012-05-21 11:07

dsPIC® High-Performance 16-bit Digital Signal Controller Family:
Operating Range:
• DC – 30 MIPS (30 MIPS @ 4.5-5.5V, -40 to 85°C)
• Wide VDD range: 2.5-5.5V
• Ind. (-40 to 85°C) and Ext. (-40 to 125°C)
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 84 base instructions: mostly 1 word/1 cycle
• 16 16-bit General Purpose Registers (GPR)
• 2 40-bit accumulators:
- With rounding and saturation options
• Flexible and powerful addressing modes:
- Indirect, Modulo and Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single cycle multiply-and-accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• 40-stage barrel shifter
Interrupt Controller:
• 5-cycle latency
• Up to 45 interrupt sources, up to 5 external
• 7 programmable priority levels
• 4 processor exceptions
Digital I/O:
• Up to 54 programmable digital I/O pins
• Wake-up/Interrupt-on-change on up to 24 pins
• 25 mA sink and source on all I/O pins
On-Chip Flash, Data EEPROM and SRAM:
• Flash program memory: up to 144 Kbytes:
- 10,000 erase/write cycles, min. (-40 to 85°C)
- 100,000 erase/write cycles, typical
• Data EEPROM: up to 4 Kbytes:
- 100,000 erase/write cycles, min. (-40 to 85°C)
- 1M erase/write cycles, typical
- Data EEPROM retention > 20 years
• Data SRAM: up to 8 Kbytes
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL (4X, 8X, 16X)
- Extremely low jitter PLL
• Programmable Power-up Timer
• Oscillator start-up timer/stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• Switch between clock sources in real time
• Programmable low-voltage detect
• Programmable Brown-out Reset
• Idle and Sleep modes with fast wake-up
Timers/Capture/Compare/PWM:
• Timer/counters: up to 5 16-bit timers:
- Can pair up to make 32-bit timers
- 1 timer can run as real-time clock with external
32 KHz oscillator
- Programmable prescaler
• Input capture: up to 8 channels:
- Capture on up, down or both edges
- 16-bit Capture input functions
- 4-deep FIFO on each capture
• Output compare: up to 8 channels:
- Single or dual 16-bit Compare mode
- 16-bit glitchless PWM mode
Communication Modules:
• 3-wire SPI™: up to 2 modules:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™ full multi-master Slave mode support:
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
• UART: up to 2 modules:
- Interrupt-on-address bit detect
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
• Data Conversion Interface (DCI) module
- Codec interface
- Supports I2S and AC’97 protocols
- Up to 16-bit data words, up to 16 words per
frame
- 4-word deep TX and RX buffers
• CAN 2.0B active: up to 2 modules:
- 3 transmit and 2 receive buffers
- 6 receive filters and 2 masks
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
Motor Control Peripherals:
• Motor Control PWM: up to 8 channels:
- 4 duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center aligned
- Manual output override control
- Up to 2 Fault inputs
- Trigger for A/D conversions
- PWM Frequency for 16-bit resolution
(@ 30 MIPS) = 915 Hz for Edge-Aligned
mode, 457.5 Hz for Center-Aligned mode
- PWM Frequency for 11-bit resolution
(@ 30 MIPS) = 29.3 KHz for Edge-Aligned
mode, 14.65 KHz for Center-Aligned mode
Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter