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The TMS320VC5506 fixed-point digital signal processor is based on the TMS320C55x DSP generation CPU processor
core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total
focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program
bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity.
The C55x CPU provides two multiply-accumulate units, each capable of 17-bit x 17-bit multiplication in a single cycle. A
central 40-bit arithmetic/logic unit is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control,
providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address
Unit and Data Unit of the C55x CPU.
These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA
controller can perform up to two data transfers per cycle independent of the CPU activity.